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https://en.wikipedia.org/wiki/Physical_Address_Extension
In traditional 32-bit protected mode, x86 processors use a two-level page translation scheme, where the control register CR3 points to a single 4 kiB long page directory divided 1024 × 4 byte entries that point to 4 kiB long page tables, similarly consisting of 1024 × 4 byte entries pointing to 4 KiB long pages.
Enabling PAE (by setting bit 5, PAE, of the system register CR4) causes major changes to this scheme. By default, the size of each page remains as 4 kiB. Each entry in the page table and page directory grows to 64 bits (8 bytes) rather than 32 bits - to allow for additional address bits; however, the size of tables does not change, so both table and directory now have only 512 entries. Because this allows only one quarter of the entries of the original scheme, an extra level of hierarchy has been added, so CR3 now points to the Page Directory Pointer Table, a short table which contains pointers to 4 page directories.
The entries in the page directory have an additional flag in bit 7, named PS (for page size). If the system has set this bit to 1, the page directory entry does not point to a page table, but to a single large 2 MiB page. The NX bit is another flag in the page directory, in bit 63, to mark pages as no execute. Because the 12 least significant bits of the page table entry's 64 bits are either similar flags or are available for OS-specific data, a maximum of 52 bits can be potentially used in the future to address 252 bytes, or 4 petabytes, of physical memory.
